Secure integrated circuit including parts having a confidential nature and method for operating the same

ABSTRACT

The secure integrated circuit ( 1 ) further includes storage means ( 2 ) in which confidential data is stored, such as an encryption programme and at least an encryption key, and a microprocessor unit ( 3 ) for executing the encryption programme. Said circuit further includes an oscillator stage ( 4, 5 ) supplying clock signals (CLK) in particular for clocking the sequence of operations in the microprocessor unit ( 3 ), and a random number generator ( 6 ) connected to the microprocessor unit. A random number (RNGosc) generated by the random number generator is supplied to the input of the oscillator stage to configure it such that the frequency of the clock signals supplied by the oscillator stage depends on said random number. The oscillator stage includes an RC type oscillator, in which a certain number of resistors and/or capacitors can be selected by the random number introduced at the input of the oscillator stage. So the frequency of clock signals depends on the RC component selected as a function of said received random number.

[0001] The invention concerns a secure integrated circuit which includesparts of a confidential nature. The integrated circuit includes storagemeans in which confidential data is stored, such as an encryptionprogramme and at least an encryption key, a microprocessor unit forexecuting the encryption programme, an oscillator stage supplying clocksignals for clocking the flow of operations in the microprocessor unit,and a random number generator connected to the microprocessor unit. Theoscillator stage is arranged to receive at least a random numberproduced by the random number generator so as to configure saidoscillator stage so that it produces clock signals whose frequencydepends on the random number received. The confidential data concerns,in particular mathematical functions to be protected, encryptionprogrammes and personal access codes.

[0002] The invention also concerns a method for operating or activatingthe secure integrated circuit.

[0003] Secure integrated circuits are used particularly in specificelectronic devices in which data of a confidential nature has to beprotected. Said circuits can be applied for example in micro-computerunits or in hard-wired logic circuits, such as badges or smart cards orwithin encoded data transmission fields.

[0004] Within the technical field of smart cards, such as bankcards, atleast one secure integrated circuit is integrated in said card. Electriccontact pads, which are connected to the integrated circuit, are made onthe smart card so as to act as an interface with the read and/or writedevice for specific data. When the smart card is introduced into theread and/or write device, an encryption programme with an encryption keycan be executed in the microprocessor unit as soon as the integratedcircuit is switched on.

[0005] Usually, the execution time for the various instruction sequencesof the programme, and the single frequency clock signals for clockingthe operations processed in the microprocessor unit, are well defined.Consequently, unauthorised persons can fraudulently decipher severalconfidential data items relatively easily using encryption analysistechniques.

[0006] The analysis techniques used are for example of the DPA(Differential Power Analysis) type or the DFA (Differential FaultAnalysis) type. The first of these techniques consists in measuring theamplitude of the current consumed across electric contact terminals ofthe integrated circuit during all the instruction sequences of theprogramme. This allows the single frequency of the clock signals to befound, on the one hand, and on the other hand the encryption key or keysused in the encryption programme to be found. The second techniqueconsists in having the encryption programme executed several times andinterrupting it at precise moments in order to disrupt it (deterministmethod). In this way, and on the basis of the good or bad calculationresults obtained, it is possible to decode the encryption keys.

[0007] A person with ill intent can also analyse without too muchdifficulty the confidential data memory zones using a suitable testmaterial given that the integrated circuit is usually clocked by singlefrequency clock signals. In order to do this, the metal pads and theprotective passivation layer covering the secure integrated circuit haveto be removed. After removal of the protective layers, test probes areplaced on the memory zones, and several correlations between the varioustested memory zones are carried out to find the stored confidentialdata.

[0008] Several technical solutions have already been proposed to preventan ill-intentioned person from finding the confidential data viaencryption analysis techniques. One solution consists for example inslowing down or speeding up the flow of the encryption programme usingclock signals with a variable frequency. One can cite, for example,International Patent document No. WO 97/33217 which discloses a secureintegrated circuit which is provided with decorrelation means for theflow of at least one instruction sequence of a main encryptionprogramme. The integrated circuit mainly includes storage means, inwhich a main encryption programme and a secondary programme are stored,and a microprocessor unit connected to the storage means for operatingthe main programme and/or the secondary programme.

[0009] The decorrelation means of the integrated circuit include inparticular an oscillator for providing internal clock signals at aconstant frequency, and a random generator receiving the internal clocksignals or the external clock signals via a logic selection circuit. Therandom number generator supplies randomly distributed pulse signals viaa calibrator circuit to clock the operations in the microprocessor unit.It should be noted that the internal clock signals are non synchronisedand phase shifted with respect to the external clock signals so as toallow the microprocessor unit to pass to decorrelated operation.

[0010] The decorrelation means also include a timer for providinginterruption signals to the microprocessor unit to momentarily interruptthe flow of the main programme. The intervals of time between eachinterruption signal can be defined randomly by random numbers providedto the timer by the random number generator. Likewise, during aninterruption, an interruption routine or a secondary programme may beexecuted so as to prevent any analysis of the integrated circuit'sconfidential data.

[0011] One drawback of the solution disclosed in document No. WO97/33217 is that the internal clock signals are pulse signals at aconstant frequency. Thus, the random number generator, which receivesthe internal clock signals, can only provide pulse signals of variableperiodicity whose mean frequency is less than the internal clocksignals. It should be noted that randomly distributed pulse signals areonly obtained by randomly suppressing certain pulses of the internalclock signals without modifying the width of each clock pulse. In ordernot to slow down the sequence of operations of the main programme toomuch, it is thus necessary to have internal clock signals at asufficiently high frequency, which constitutes another drawback.

[0012] The main object of the present invention is to overcome thedrawbacks of the prior art by providing a secure integrated circuithaving simplified means for randomly varying the time for executing thesequence of operations of an encryption programme in order to preventencryption analysis.

[0013] The invention therefore concerns a secure integrated circuit ofthe aforementioned type, wherein the oscillator stage includes an RCtype oscillator, and wherein a certain number of resistors and/orcapacitors can be selected by the random number introduced at the inputof the oscillator stage so as to generate clock signals whose frequencydepends on the RC component selected as a function of said receivedrandom number.

[0014] One advantage of the secure integrated circuit according to theinvention is that the oscillator stage can easily be configured usingeach random number received successively in order to produce clocksignals with a random frequency. This allows the frequency of the clocksignals for clocking the operations of the microprocessor unit to berapidly changed. Each time that the secure integrated circuit isswitched on or when the encryption programme is executed, the frequencyof the clock signals will change, since the random number generator willprovide a random number to the oscillator stage, said random numberbeing different from the preceding random number generated.

[0015] Another advantage of the secure integrated circuit according tothe invention is that the clock signals provided by the oscillator stageare regular rectangular pulse signals, i.e. the space between two pulsesis substantially identical to the width of each pulse. Consequently,each random number provided to the input of the oscillator stage willhave an equivalent influence on the width of the pulses and on the gapseparating two pulses. In order to limit the use of external clocksignals upon introduction, for example, of a secure smart card into aread and/or write device, the frequency of the internal clock signals isadjusted to a higher value than the frequency of the external signals.

[0016] Another advantage of the secure integrated circuit according tothe invention is that a timer supplies interruption signals to themicroprocessor unit in order to interrupt the sequence of operations ofthe encryption programme. The interruptions to the sequence ofoperations of the programme can be made in a random manner if the timerreceives a random number from the random number generator. Moreover,each interruption signal can be provided on the basis of a certainnumber of pulses of the random frequency clock signals. The number ofpulses counted in the timer can be dependent on the random numberreceived by the timer. Thus, the time for executing the sequence ofoperations of the programme cannot be determined precisely, whichprevents encryption analysis of the secure integrated circuit.

[0017] Upon reception of an interruption signal, the microprocessor unitmay also execute an interruption routine between instruction sequencesof the encryption programme. As soon as the interruption signal isreceived, the microprocessor unit can command the transmission of arandom number to the oscillator stage in order for it to produce a clocksignal frequency change.

[0018] The invention also concerns a method for activating the secureintegrated circuit of the aforecited type, which includes the steps of:

[0019] generating at least one random number in the random numbergenerator,

[0020] transmitting said random number generated to the oscillatorstage, which includes an RC type oscillator, in which a certain numberof resistors and/or capacitors can be selected by the random numberintroduced at the input of the oscillator stage,

[0021] producing clock signals in the oscillator stage whose frequencydepends on the RC component selected as a function of said random numberreceived in order to clock the sequence of operations in themicroprocessor unit.

[0022] The objects, advantages and features of the secure integratedcircuit will appear more clearly in the following description ofembodiments illustrated by the drawings in which:

[0023]FIG. 1 shows schematically the functional units of the secureintegrated circuit according to the invention,

[0024]FIG. 2a shows various electronic elements forming the oscillatorstage of the secure integrated circuit according to the invention,

[0025]FIG. 2b shows the components of a bistable trigger circuit forgenerating rectangular pulse signals of the oscillator stage shown inFIG. 2a, and

[0026]FIG. 3 shows a flow diagram of the sequence of operations duringthe execution of the encryption programme in the microprocessor unit ofthe secure integrated circuit according to the invention.

[0027] The following description will not describe in detail all thecomponents or electronic units of the secure integrated circuit whichare well known to those skilled in the art in this technical field. Onlythe components or electronic units of the oscillator stage will bedescribed in more detail.

[0028] The various essential units, included in the secure integratedcircuit, are shown in FIG. 1. Secure integrated circuit 1 includes firstof all storage means 2 in which are stored, in particular, an encryptionprogramme and at least an encryption key, and a microprocessor unit 3connected via a data bus 8 to the storage means, said unit allowing theencryption programme to be executed using the encryption key.

[0029] The encryption programme is, for example, a DES type algorithmwell known to the experts in this technical field. This programme isstored in particular in a non-volatile ROM memory 2 a. An EEPROM memory2 b is also provided in storage means 2 for storing several data itemswhen the encryption programme is executed or for keeping confidentialdata, such as personal access codes or encryption keys. The encryptionkey or keys are used during execution of the encryption programme by themicroprocessor unit. Of course, storage means 2 can include other typesof memories, such as a Flash memory or a RAM type memory, not shown inFIG. 1.

[0030] The secure integrated circuit also includes a random numbergenerator 6 connected via a bus RNG to microprocessor unit 3, and anoscillator stage which is formed of a register 4 for receiving a randomnumber transmitted by microprocessor unit 3 via bus RNGosc, and an RCtype oscillator 5 supplying clock signals CLK particularly to themicroprocessor unit. Addressing, reading and/or writing of the storagemeans can be clocked directly by clock signals CLK or by signalsoriginating from a clock signal control device of the microprocessorunit. The integrated circuit also includes a timer 7 intended to provideinterruption signals INT to the microprocessor unit to momentarilyinterrupt the operations processed in said unit.

[0031] In order to prevent encryption analysis, the frequency of theclock signals CLK generated by oscillator stage 4, 5 has to be able tovary randomly. In normal operation, i.e. particularly during executionof the encryption programme, the oscillator stage can be configured byrandom numbers so as to generate clock signals whose frequency is withina frequency range of between 13 and 20 MHz. However, for themicroprocessor unit, it is preferable for the frequency not to exceed 24MHz. Thus, the microprocessor unit can include a clock signal controldevice which allows frequency divisions to be carried out for certainprocessed operations or the clock signals CLK to be directed to timer 7or storage means 2.

[0032] It may still be desirable, in operating periods of the integratedcircuit without execution of the encryption programme, for the frequencyof the clock signals produced by the oscillator stage to be fixed at alow value, such as at 1.25 MHz. In this case, the oscillator stage isconfigured to produce only fixed low frequency clock signalsindependently of a random number introduced into the oscillator stageregister. This frequency reduction saves on the current consumed by theintegrated circuit. Likewise, in order to reduce consumption in certainoperating periods of the secure integrated circuit, the random numbergenerator and/or the timer can be momentarily deactivated.

[0033] The frequency variation can occur each time the circuit isswitched on, during execution of the encryption programme in themicroprocessor unit, or upon reception of an interruption signal in themicroprocessor unit, or each time a random number is supplied fromrandom number generator 6. Oscillator 5 which forms said oscillatorstage will be explained in more detail hereinafter with reference toFIGS. 2a and 2 b.

[0034] Random number generator 6 is usually used for example in theauthentification processes of the circuit or for encryption functions.The generator, well known in this technical field, can be formed of anindependent non-synchronised oscillator of the oscillator stage, of apseudo-random counter clocked by the non-synchronised clock signals, andan output register connected to the counter for providing random numbersat each loading pulse. The non-synchronised clock signal frequency iswithin the range of 30 to 90 kHz.

[0035] The random numbers generated by the generator are binary words,which can be limited to 8 bits. Via a read instruction EN from themicroprocessor, the random numbers are first of all transmitted to themicroprocessor unit via the random number bus RNG. Next, themicroprocessor unit transmits via bus RNGosc at least one receivedrandom number in order to load, particularly, register 4 of theoscillator stage for the frequency variation of clock signals CLK.

[0036] The supply of successive random numbers to register 4 of theoscillator stage can be controlled by the microprocessor unit, inparticular during the encryption programme executing period in saidunit. Microprocessor unit 3 may also transmit all the received randomnumbers to register 4.

[0037] In an embodiment that is not shown, the oscillator stage canreceive successively random numbers which originate directly from therandom number generator.

[0038] Timer 7 is clocked by the clock signals whose frequency varies asa function of a random number provided in register 4 of the oscillatorstage. After a certain number of clock pulses CLK received viamicroprocessor unit 3, the timer produces an interruption signal whichit sends via bus INT to microprocessor unit 3 in order to momentarilyinterrupt the operations processed in said unit.

[0039] Timer 7 can also receive random numbers via microprocessor unit 3such that the interval between two interruption signals varies in arandom manner. It may be imagined that a random number introduced intothe timer influences the number of received clock signals CLK whichtrigger an interruption signal. Consequently, the interruptions areprovided randomly to the microprocessor unit.

[0040] Thus the interruptions of the encryption programme in themicroprocessor unit also allows to prevent a person to find out theconfidential data of the secure integrated circuit. For example at least16 interruptions and at the most 32 interruptions of the encryptionprogramme executed in the microprocessor unit can be provided.

[0041] As will be explained with reference to FIG. 3, it is alsoprovided that, during an interruption to the encryption programme, aninterruption routine is executed in the microprocessor unit. Thisroutine randomly adds instruction sequences in the interruptedencryption programme, which prevents an execution time of the executedprogramme from being precisely defined. Moreover, variations in thecurrent consumed during execution of the encryption programme andinterruption routine are produced by randomly imposing data storage orreading of the storage means. Consequently, encryption analysis forexample of the DPA type cannot be carried out to find the confidentialcontent of the secure integrated circuit which constitutes an object tobe achieved by the integrated circuit of the present invention.

[0042] The oscillator stage will now be explained in more detail withreference to FIGS. 2a and 2 b. This stage is connected to a regulatedvoltage source between two potential terminals Vdd and Vss. PotentialVdd has a value lower than 3 V, preferably 2.8 V, whereas potential Vsshas a value of 0 V, which corresponds to the earth terminal of theintegrated circuit.

[0043] The RC type oscillator of the oscillator stage includes a set ofresistors Rosc. A binary word TRIM originating from the oscillator stageregister configures this set of resistors. This binary word correspondsto a random number placed in said register.

[0044] The set of resistors is arranged to place a certain number ofresistors that can be selected in parallel or in series owing toswitching elements such as NMOS or PMOS transistors that are not shown.The gate of each transistor can be controlled by a voltage as functionof binary word TRIM received from the register so as to make thecorresponding transistor conductive or non conductive, and to connectresistors in parallel or in series. The resistor value chosen by binaryword TRIM determines with a capacitor Cosc the frequency value of clocksignals CLK generated at the oscillator output.

[0045] The configured set of resistors Rosc allows current sources to begenerated in a first current mirror connected to a positive potentialterminal Vdd, and in a second current mirror connected to a negativepotential terminal Vss. Said set is thus placed in series between thetwo current mirrors.

[0046] The first current mirror includes a first PMOS transistor P1 anda second PMOS transistor P2, as well as a fourth PMOS transistor P4which will be explained with reference to FIG. 2b. Gate Bp and the drainof first transistor P1 are connected to a positive terminal of set ofresistors Rosc, and the source of transistor P1 is connected to terminalVdd. The gate of second transistor P2 is connected to the gate Bp offirst transistor P1, and the source of the second transistor P2 isconnected to the terminal Vdd. The drain of the second transistor isconnected to the source of a third PMOS transistor P3.

[0047] The second current mirror includes a first NMOS transistor N1 anda second NMOS transistor N2, as well as a fourth NMOS transistor N4which will be explained with reference to FIG. 2b. Gate Bn and the drainof first transistor N1 are connected to a negative terminal of set ofresistors Rosc, and the source of transistor N1 is connected to terminalVss. The gate of second transistor P2 is connected to the gate Bn offirst transistor N1, and the source of the second transistor N2 isconnected to the terminal Vss. The drain of the second transistor N2 isconnected to the source of a third NMOS transistor N3.

[0048] The third transistors P3 and N3 each have their drain connectedto a positive terminal of a capacitor Cosc, whose negative terminal isconnected to Vss. The gates of these two third transistors P3 and N3 areconnected to each other. If the potential of gates P3 and N3, connectedto the output of clock signals CLK, is close to Vdd, transistor P3 isnon conductive, whereas transistor N3 becomes conductive to allow thecurrent duplicated from the second current mirror to pass. CapacitorCosc is thus discharged owing to the current duplicated in the secondcurrent mirror dependent on set of resistors Rosc. If the potential ofthe gates of transistors P3 and N3, connected to the output of clocksignals CLK, is close to Vss, transistor N3 is non conductive, whereastransistor P3 becomes conductive to allow the current duplicated by thefirst current mirror to pass. Capacitor Cosc is thus charged owing tothe current duplicated in the first current mirror dependent on set ofresistors Rosc.

[0049] It will be understood that the signals, originating from thecharging and discharging of capacitor Cosc, are triangular signals. Itis thus indispensable to convert the triangular signals into rectangularpulse signals. This conversion is carried out in particular by abistable trigger circuit ST or Schmitt trigger circuit. The input in ofthis circuit ST is connected to the positive terminal of capacitor Cosc,as well as to the drains of transistors P3 and N3, whereas the outputout of this circuit ST is connected to two inverters in series INV1 andINV2. Clock signals CLK with substantially rectangular pulses areprovided at the output of second inverter INV2. It is to be noted that acertain signal transition delay between output out and output CLK isachieved owing to the two inverters INV1 and INV2.

[0050] The output out of Schmitt trigger circuit ST is at the high statewhen capacitor Cosc is discharged. In this case, transistor N3 isconductive, whereas transistor P3 is non conductive so that the currentduplicated by the second current mirror discharges capacitor Cosc. Thisdischarging of Cosc is carried out until the potential of said capacitorCosc reaches a first low threshold level detected by circuit ST at inputin. As soon as the potential of capacitor Cosc has reached the firstthreshold level, the output out of circuit ST passes to the low state.From this instant, the transition of signals at output out of circuit STimposes a transition of clock signals CLK from the high state to the lowstate.

[0051] The passage of clock signals CLK from the high state to the lowstate will allow transistor N3 to be blocked and transistor P3 to beopened in order to charge capacitor Cosc using the current duplicated inthe first current mirror. Capacitor Cosc will thus be charged until thepotential of said capacitor Cosc reaches a second high threshold leveldetected by circuit ST at input in. As soon as the potential ofcapacitor Cosc has reached the second threshold level, output out ofcircuit ST passes to the high state. From this instant, the transitionof the signals at output out of circuit ST imposes a transition of clocksignals CLK from the low state to the high state.

[0052]FIG. 2b shows Schmitt trigger circuit ST. The fourth PMOS and NMOStransistors P4 and N4 have their gates respectively connected to gate Bpof the first current mirror, and to gate Bn of the second currentmirror. The source of fourth transistor P4 is connected to terminal Vdd,whereas the source of fourth transistor N4 is connected to terminal Vss.The drain of transistor P4 is connected to the source of a sixth PMOStransistor P6 to provide it with the current duplicated in the firstcurrent mirror, whereas the drain of transistor N4 is connected to thesource of a sixth NMOS transistor N6 to provide it with the currentduplicated in the second current mirror.

[0053] Transistors P6 and N6 have their gates respectively connected toinput in of the Schmitt trigger circuit, and their drains connected tothe input of a third inverter INV3. The output of third inverter INV3 isconnected to output out of the Schmitt trigger circuit, as well as tothe gate of a fifth PMOS transistor P5 and to the gate of a fifth NMOStransistor N5. The source of fifth transistor P5 is connected toterminal Vdd, whereas its drain is connected to the source of sixthtransistor P6. The source of fifth transistor N5 is connected toterminal VSS, whereas its drain is connected to the source of sixthtransistor N6.

[0054] When output out passes to the high state, transistor P5 isblocked, whereas transistor N5 is conductive. Consequently, the input ofinverter INV3 is at the low state since transistors N6 and N5 areconductive in capacitor Cosc's discharging phase. The potential appliedto input in of circuit ST decreases linearly in capacitor Cosc'sdischarging phase. When the potential at input in of circuit ST is closeto Vdd/2, transistor P6 becomes conductive allowing the currentduplicated in the first current mirror to pass. However, sincetransistor N5 is fully conductive, it totally absorbs the well-definedcurrent provided by transistor P6 through conductive transistor N6.Thus, the potential at input in could decrease as far as the first lowthreshold level defined approximately by the threshold voltage oftransistor N6 before output out passes from the high state to the lowstate.

[0055] When output out passes to the low state, transistor N5 is nonconductive, whereas transistor P5 is conductive. Consequently, the inputof inverter INV3 is at the high state since transistors P6 and P5 areconductive in capacitor Cosc's charging phase. The potential applied toinput in of circuit ST increases linearly in capacitor Cosc's chargingphase. When the potential at input in of circuit ST is close to Vdd/2,transistor N6 becomes conductive allowing the current in the secondcurrent mirror to pass. However, since transistor P5 is fullyconductive, it totally absorbs the well-defined current provided bytransistor N6 through conductive transistor P6. Thus, the potential atinput in could increase as far as the second high threshold leveldefined approximately by the threshold voltage of transistor P6 beforeoutput out passes from the low state to the high state.

[0056] Owing to the Schmitt trigger circuit, the clock signals aresubstantially rectangular pulse signals.

[0057]FIG. 3 shows a flow chart of the sequence of operations during theexecution of the encryption programme in the microprocessor unit.

[0058] As soon as the secure integrated circuit is switched on or when asubsequent encryption programme is chosen for execution, the DES typeencryption programme is executed by the microprocessor unit at step 10.It is to be noted that the encryption programme activated selection isfor example achieved by an external command sent to the secureintegrated circuit. A random number is read by the microprocessor unitin the register of the random number generator at step 11. This randomnumber is loaded in register TRIM of the stage oscillator at step 12 bythe microprocessor unit. The oscillator stage will thus produce clocksignals whose frequency depends on the random number received. Themicroprocessor unit will then read another random number in the registerof the random number generator at step 13 and transmit it to the timerat step 14. It is clear that the same random number could be loaded atthe same time in the oscillator stage register and in the timer. Duringexecution of the DES type encryption programme in the microprocessorunit in step 15, the timer will transmit an interruption signal at arandomly chosen instant as a function of the random number received.

[0059] As soon as the encryption programme is momentarily interrupted, asecondary routine or programme begins and a random number is read by themicroprocessor unit at step 16. At step 17, this random number is loadedinto register TRIM of the oscillator stage to replace a preceding randomnumber. Thus, the oscillator stage produces clock signals whose newfrequency depends on the new random number received. At step 18, anotherrandom number is read by the microprocessor unit. After such reading andas a function of the random number read, there is randomly, either awrite operation in the EEPROM memory at step 19, or no write operationin the EEPROM memory at step 20. Since writing in the EEPROM memoryduring executed interruption routine is random which generates anadditional current loss during writing, this consequently makes anyencryption analysis by an unauthorised person more difficult.

[0060] After this, another random number is read by the microprocessorunit at step 21. This random number is loaded into the timer at step 22,which will change the time between each interruption signal produced bythe timer. The encryption programme can again continue to be executed inthe microprocessor unit after this step 22. Until said programme iscompleted, the interruption routine can be executed several times, butthis interruption routine is not executed each time that an interruptionsignal is sent to the microprocessor unit.

[0061] From the description which has just been given, multiple variantsof the secure integrated circuit can be conceived by those skilled inthe art, without departing from the scope of the invention. For example,in the oscillator stage, the set of resistors may be replaced by a fixedresistor and the fixed capacitor may be replaced by a set of capacitors.This set of capacitors can be configured by a binary word TRIMoriginating from the oscillator stage register, as it was the case forthe set of resistors. This binary word corresponds to a random numberplaced in said register.

[0062] The configuration of the set of capacitors consists in placing acertain number of capacitors that can be selected in parallel or inseries owing to switching elements controlled, for example, by a voltagewhich is a function of binary word TRIM.

1.-14. (canceled).
 15. A secure integrated circuit including storagemeans in which confidential data is stored, such as an encryptionprogramme and at least an encryption key, a microprocessor unit forexecuting the encryption programme, an oscillator stage supplying clocksignals for clocking the sequence of operations in the microprocessorunit, and a random number generator connected to the microprocessorunit, the oscillator stage being arranged to receive at least a randomnumber generated by the random number generator so as to configure saidoscillator stage so that it generates clock signals, whose frequencydepends on the random number received, wherein the oscillator stageincludes an RC type oscillator, and wherein a certain number ofresistors and/or capacitors can be selected by the random numberintroduced at the input of the oscillator stage so as to generate clocksignals whose frequency depends on the RC component selected as afunction of said received random number.
 16. The integrated circuitaccording to claim 15, wherein the oscillator stage receives at least arandom number generated by the random number generator via themicroprocessor unit.
 17. The integrated circuit according to claim 15,wherein, during the execution of the encryption programme in themicroprocessor unit, the oscillator stage is arranged to receive severalsuccessive random numbers at different time intervals so that thefrequency of the clock signals changes as a function of each randomnumber received.
 18. The integrated circuit according to claim 15,wherein each random number, generated by the random number generator andprovided to the oscillator stage, is placed in a calibrating register ofsaid oscillator stage.
 19. The integrated circuit according to claim 18,wherein a set of resistors is placed in series between a first currentmirror connected to a positive potential terminal of a voltage source,and a second current mirror connected to a negative potential terminalof said voltage source, the value of the resistor selected determiningthe value of the current to be duplicated in the first and secondcurrent mirrors, wherein a capacitor is charged or discharged by thecurrent duplicated in the first current mirror or in the second currentmirror so as to produce triangular signals, wherein a Schmitt triggercircuit is connected to the capacitor in order to provide at outputclock signals with rectangular pulses as a function of the triangularsignals, said clock signals controlling switching elements so that thecapacitor is charged by a current duplicated in the first current mirrorwhen the potential of the clock signals is at the low state and so thatthe capacitor is discharged by the current duplicated in the secondcurrent mirror when the potential of the clock signals is at the highstate.
 20. The integrated circuit according to claim 15, wherein itincludes a timer connected to the microprocessor unit, said timersupplying at least one interruption signal to the microprocessor unit tomomentarily interrupt the sequence of operations processed in themicroprocessor unit.
 21. The integrated circuit according to claim 20,wherein, when the encryption programme is executed in the microprocessorunit, the timer supplies several interruption signals at separate timeintervals.
 22. The integrated circuit according to claim 20, wherein thetimer receives random numbers at separate time intervals, said randomnumbers being generated by the random number generator and supplied tothe microprocessor unit such that the timer supplies the microprocessorunit with a certain number of interruption signals wherein the intervalbetween each interruption signal depends on the random number received.23. The integrated circuit according to claim 20, wherein, when theencryption programme is executed in the microprocessor unit, aninterruption routine is executed as soon as at least one interruptionsignal is provided to the microprocessor unit so as to add instructionsequences randomly to the encryption programme, and wherein a randomnumber is provided to the oscillator stage as soon as at least oneinterruption signal is transmitted to the microprocessor unit.
 24. Theintegrated circuit according to claim 20, wherein the timer is clockedby the clock signals provided by the oscillator stage, and wherein thetime interval between the interruption signals is defined by adetermined number of clock signal pulses as a function of a randomnumber received by the timer.
 25. A method for activating a secureintegrated circuit according to claim 15, the circuit including storagemeans in which confidential data is stored, such as an encryptionprogramme and at least an encryption key, a microprocessor unit forexecuting the encryption programme, an oscillator stage supplying clocksignals for clocking the sequence of operations in the microprocessorunit, and a random number generator connected to the microprocessorunit, the oscillator stage being arranged to receive at least a randomnumber generated by the random number generator so as to configure saidoscillator stage so that it generates clock signals, whose frequencydepends on the random number received, wherein the method includes thesteps of: generating at least one random number in the random numbergenerator, transmitting said random number generated to the oscillatorstage, which includes an RC type oscillator, in which a certain numberof resistors and/or capacitors can be selected by the random numberintroduced at the input of the oscillator stage, producing clock signalsin the oscillator stage whose frequency depends on the RC componentselected as a function of said random number received in order to clockthe sequence of operations in the microprocessor unit.
 26. The methodaccording to claim 25, wherein the microprocessor unit sends a readinstruction to the generator so that it provides the microprocessor unitwith at least a generated random number, and wherein the microprocessorunit transmits the random number read to the oscillator stage.
 27. Themethod according to claim 26, wherein, when the encryption programme isexecuted in the microprocessor unit, several random numbers aresuccessively generated by the generator, wherein the microprocessor unitsuccessively reads the random numbers generated by the generator atdifferent time intervals, and wherein each random number is successivelytransmitted to the oscillator stage to configure it such that itgenerates clock signals whose frequency changes as a function of eachrandom number received.
 28. The method according to claim 25, whereininterruption signals of the sequence of operations of the encryptionprogramme in the microprocessor unit are provided by a timer at timeintervals varying randomly as a function of a random number receivedand/or as a function of clock signals provided by the oscillator stage,and wherein an interruption routine is executed as soon as at least oneinterruption signal is provided to the microprocessor unit so as to addinstruction sequences randomly to the encryption programme.